arXiv cs.AI· David Rostcheck·· 11 小时前AI 评分23
用高层 Vitis HLS 打通 AWS 云端 FPGA 开发流程
Enabling AWS Cloud FPGA Development Using High-Level Vitis HLS
AI 导读
研究团队发布了一套从高层语言开发 AWS EC2 F2 云端 FPGA 机器学习模型的工具链，补上了 Vitis HLS 到 HDK 再到 AFI 的完整流程。
正文 · 原文
Abstract:We present a toolchain for development of ML models on AWS EC2 F2 cloud FPGA infrastructure from high-level language, implementing a complete Vitis HLS to HDK bridge to AFI workflow that has been absent from the academic literature despite eight years of AWS FPGA availability. We introduce a four-level methodology (FP32 PyTorch, bit-accurate quantized Python, HLS C-simulation, physical FPGA) to aid in localizing errors, including FPGA-specific circuit errors. Together these tools allow coding agents to effectively implement FPGA designs from user directions, testing and debugging as needed. We document the deployment workflow, timing closure strategies, and practical HLS engineering decisions that proved crucial. We validate using TinyBERT fine-tuned for address Named Entity Recognition, implementing the embedding layer and the first of four encoder layers on the FPGA hardware. Our implementation streams weights from host DRAM, yielding poor performance compared to CPU/GPU implementations; we discuss forward paths.
| Subjects: | Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG) |
| Cite as: | arXiv:2611.06829 [cs.AR] |
| (or arXiv:2611.06829v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2611.06829 arXiv-issued DOI via DataCite (pending registration) |
Submission history
From: David Rostcheck [view email]
[v1]
Wed, 4 Nov 2026 17:44:04 UTC (41 KB)
来源：arXiv cs.AI · arxiv.org