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arXiv cs.AI· Fatemeh Bahrami, Seyed-Hosein Attarzadeh-Niaki·· 3 天前AI 评分15

SafeDSE:面向数据流应用的安全架构模式、映射与调度联合探索及安全论证

SafeDSE: Joint Exploration of Safety Architecture Patterns, Mapping, and Scheduling for Dataflow Applications With Safety Arguments (Extended Version)

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SafeDSE 是一个面向同步数据流应用的设计空间探索框架,用单一声明式约束模型同时决定每个 actor 的模式、故障模型要求的放置、静态顺序调度与平台,并对 SIL 提升定价。

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Abstract:Embedded platforms increasingly host safety-related streaming functions next to less critical ones. Whether a safety architecture pattern, such as a doer/checker pair, protects a function depends on the cores that run its components. Their schedule must meet the throughput requirement, and mixing safety integrity levels (SILs) on one core raises development cost. This report presents SafeDSE, a design space exploration framework for synchronous dataflow applications. One declarative constraint model decides the pattern of each actor, the placement that the fault model requires, the static-order schedule, and the platform, and prices SIL promotion. Guards activate the chosen patterns in a fixed graph that holds all of them, and node potentials encode throughput. An independent verifier re-checks every solution, and a generator turns its checks into evidence of a safety argument in Goal Structuring Notation. On 9 benchmark instances under period bounds, no rule that fixes patterns before mapping was both always feasible and never more expensive under conservative pricing, while joint exploration was. In the generated arguments, 49 to 62% of the leaves cite verifier checks; the rest are claims a mapping cannot discharge. Optimality within the model was proven for all synthetic graphs with up to 16 actors. This extended version adds the full model, the verifier and generator in detail, the complete catalog and parameters, and a proof of the potential characterization. It also reports every experiment per instance, a mutation analysis of the verifier, and the negative results of the development.
Comments: 38 pages, 12 figures, 29 tables. Extended version of a paper submitted for publication; tool and data at this http URL
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Logic in Computer Science (cs.LO); Software Engineering (cs.SE)
Cite as: arXiv:2610.16213 [cs.AR]
  (or arXiv:2610.16213v1 [cs.AR] for this version)
  https://doi.org/10.48550/arXiv.2610.16213

arXiv-issued DOI via DataCite (pending registration)

Submission history

From: Seyed-Hosein Attarzadeh-Niaki [view email]
[v1] Mon, 12 Oct 2026 05:43:56 UTC (664 KB)

来源:arXiv cs.AI · arxiv.org