arXiv cs.AI· Saeid Rajabi, Aly Moussa, Vishal Saxena, Chengmo Yang, Satwik Patnaik·· 13 小时前AI 评分31
AnalogPortBench：评测 LLM 模拟电路移植能力的基准
AnalogPortBench: Benchmarking LLMs on Analog Circuit Porting
AI 导读
研究者推出 AnalogPortBench，包含 54 个任务，将十种电路（从电流镜到伸缩式放大器）从 0.18 μm 工艺移植到开源 SKY130 PDK。评测六个前沿 LLM 在两种推理水平、有无仿真反馈下的表现，发现模型能移植简单电路，但很少重新设计对电压余量敏感的放大器，也极少识别不可行规格，且从仿真反馈中获益多于增加采样或推理。代码与数据已公开。
正文 · 原文
Abstract:Analog circuit design still relies heavily on expert knowledge, and porting proven designs to new process nodes is a recurring bottleneck. As a lower supply reduces available voltage headroom, a working topology may require redesign or fail to meet specifications. While large language models (LLMs) have begun to generate and optimize analog circuits, existing benchmarks focus on one process node and assume feasible specifications. To bridge this gap, we introduce AnalogPortBench, a benchmark of 54 tasks for porting ten circuits, from current mirrors to telescopic amplifiers, from a 0.18 $\mu$m process to the open-source SKY130 PDK. Tasks range from a direct port through a reduced supply and harder specifications to infeasible ones, and every feasible task has a reference design verified at five process corners. Evaluating six frontier LLMs at two reasoning levels, with and without simulation feedback, we find that models port simple circuits but rarely re-design headroom-sensitive amplifiers, seldom recognize infeasible specifications, and gain more from simulation feedback than from more samples or reasoning. Code and data are available at this https URL.
| Comments: | 5 pages, 3 figures, 4 tables Code and data: this https URL |
| Subjects: | Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI) |
| Cite as: | arXiv:2610.33088 [cs.AR] |
| (or arXiv:2610.33088v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2610.33088 arXiv-issued DOI via DataCite |
Submission history
From: Saeid Rajabi [view email]
[v1]
Wed, 21 Oct 2026 20:45:51 UTC (275 KB)
来源：arXiv cs.AI · arxiv.org