arXiv cs.AI· Leo Itoh, Junichiro Kadomoto·· 14 小时前AI 评分39
基于 LLM Agent 的 RISC-V CPU 设计：FPGA 在环评估
LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
AI 导读
研究团队搭建了一套开发环境，让 LLM Agent 在 FPGA 上实现 CPU 候选设计，并用板载性能测量指导设计决策，在人工监督下将单周期 RV32I 核演进为三发射乱序 RV32IM 核。
正文 · 原文
Abstract:Long-run RTL simulation of CPU candidates can take hours, while short diagnostic runs may miss performance degradation that emerges later in execution. This evaluation cost can delay design decisions in LLM-agent-based CPU development. We present a development environment in which LLM agents implement CPU candidates on an FPGA and use on-board performance measurements to guide design decisions. We applied it to the human-supervised development of a single-cycle RV32I core into a three-wide out-of-order RV32IM core. The final design reaches 5.61 CoreMark/MHz at 130 MHz on a Artix-7 FPGA. For the same CPU candidate running 8,000 CoreMark iterations, FPGA evaluation, including implementation, was 9.6x faster than single-threaded RTL simulation. In one case, board measurements revealed long-run performance degradation in a candidate that improved in a short diagnostic run. The result guided candidate selection and led to RTL-based root-cause analysis and a fix.
| Comments: | 5 pages, 6 figures, 2 tables. Submitted to IEEE ISCAS 2027. Code and data: this https URL |
| Subjects: | Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI) |
| Cite as: | arXiv:2610.39570 [cs.AR] |
| (or arXiv:2610.39570v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2610.39570 arXiv-issued DOI via DataCite |
Submission history
From: Leo Itoh [view email]
[v1]
Thu, 29 Oct 2026 08:14:01 UTC (579 KB)
来源：arXiv cs.AI · arxiv.org